In conventional chip bonding, ceramic carriers, typically alumina, have been used as the substrate. However, the need for high-density interconnects in cost-effective chip packaging has been a motivation for using organic laminates. In contrast to ceramic substrates, organic laminates have better electrical performance at lower cost. However, when organic laminates are used for the chip assembly, incoming laminate warpage may lead to cracking or delamination of layers on the chip during the chip assembly process. Also, the warpage often results in oddly shaped solder bumps, which causes additional stress on the chip package and, possible failure of the BEOL structures such as, for example, cracking or delamination of layers, also known as white bumps. It is known incoming laminate warpage occurs due to the asymmetry of the laminates.
During the chip assembly process, the Si chip and the organic laminates also experience a temperature cycle from room temperature to the melting temperature of solder materials back to room temperature during cool down. The coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic laminate creates thermally-induced stress/strain in the flip-chip structure during the chip assembly process. The thermally-induced stress/strain in the flip-chip structure also often results in a failure of the BEOL structure. This failure is becoming more common because of the fragility of low-k dielectric layers and the use of lead-free solders.
More specifically, due to the thermal expansion mismatch between organic laminates (approximately 17×10−6/° C.) and silicon chips (approximately 2.6×10 −6/° C.), there are stresses produced during cool-down of the modules from the chip join temperature. In a die with fragile low-k dielectric materials in the BEOL, coupled with lead-free bump metallurgies which are stiffer than leaded bumps, the result is ultra-low dielectric constant (ULK) cracking on cool-down, i.e., “white bumps” observed by CSAM (Scanning Acoustic Microscopy in C mode).
“White bumps”/ULK cracking is a very serious problem which needs to be resolved in order to successfully implement lead-free bump technology on organic packages for 32 nm silicon technology nodes and beyond. However, when the white bump occurs in a chip, it is not clear if it is contributed by warpage or by CTE mismatch, or some other factors. Such determination would be an important factor in laminate design.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.